AD6641BCPZRL7-500

The AD6641 is a 250 MHz bandwidth digital predistortion observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, or a 12-bit parallel CMOS or 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold, and voltage reference are included on the chip to provide a complete signal conversion solution. The on-chip FIFO allows for small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL± pins. In the continuous capture mode, the data is loaded constantly into the FIFO and the FILL± pins are used to stop this operation.