The Si5362A is ultra-high-performance jitter attenuator that combines 2 x fifth-generation DSPLLs™ and 1 x MultiSynths™ to enable any-frequency clock generation and jitter attenuation for high performance applications like 112/224G PAM4 SerDes and OTN applications. The device has 18 outputs with an ultra-low jitter of 55 fs and a frequency output range up to 1.3GHz with a 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level. The Si5362A can be quickly and easily configured using ClockBuilder Pro software.
