SI5383B-D10546-GMR

The Si5383B clock, with internal servo algorithm, paired with the Si5388-SW protocol stack is a complete IEEE 1588 and SyncE solution targeting applications that use a centralized “pizza box” architecture.  The Si5383B is a network synchronizer clock for Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. Utilizing fourth-generation DSPLL technology, the Si5383B provides any-frequency clock generation and jitter attenuation for applications requiring the highest level of jitter performance. No external loop filter components are required and the  PLL bandwidth is digitally programmable to values as low as 0.001 Hz. With phase jitter as low as 0.15 ps RMS, the Si5383B accepts 5 clock inputs ranging from 0.000001 - 750 MHz and generates up to 7 clock output frequencies ranging from 0.000001 MHz to 350 MHz. The Si5383B meets all of the requirements specified by ITU-T G.8262 EEC Options 1 & 2, ITU-T G.8262.1, G.812 Type III & IV, G.813 Option 1, and Telcordia GR-1244 and GR-253 (Stratum 3/3E). When used with external IEEE 1588 stack and servo loop software, the Si5388A meets the requirements of ITU-T G.8273.1 and G.8273.2 (T-BC, T-TSC).