The Si5518G is optimized for 5G wireless applications which demand the highest level of integration and phase noise performance with low power consumption that reduces the total solution cost. This highly integrated digital solution eliminates external loop filter components and has high immunity to external board disturbances such as power supply noise. The DSPLL bandwidth is digitally programmable to values as low as 0.001 Hz. With phase jitter as low as 47 fs RMS, the Si5518G accepts 4/6 inputs clock ranging from 0.008 - 1000 MHz differential and PPS/PP2S, 8kHz to 250MHz for CMOS. Si5518G generates up to 18 clock outputs that are configurable in any combination of DCLK, SYSREF or other system clocks. Each output supports delay/skew adjust and frequencies ranging from PPS/PP2S up to 3200 MHz.
